The present invention relates to a semiconductor device, and more particularly to a current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter for converting a CML level signal into a CMOS level signal. More specifically, the present invention relates to a CML-CMOS converter that can prevent a duty ratio from changing in a conversion process.
In a semiconductor device, a CML level signal is generally used as an input/output (I/O) interface signal for a high-speed signal such as a clock signal. The CML level means an average level determined by a predetermined direct current (DC) level or a specified reference. The CML level signal is a signal toggling with a predetermined amplitude or a predetermined swing range around a predetermined DC level called the CML level.
For example, in an apparatus for inputting/outputting the CML level signal, when a power supply voltage (VDD) level is 1.5 V and a ground voltage (VSS) level is 0 V, a CML level of the CML level signal is 1.25 V and a swing range thereof is 0.5 V.
Since the swing range of the CML level signal is relatively small as compared with a difference between the power supply voltage (VDD) level and the ground voltage (VSS) level in the apparatus for inputting/outputting the CML level signal, the apparatus for inputting/outputting the CML level signal can operate with a relatively low power supply and can operate with a very high switching speed of GHz or tens of GHz.
Since the apparatus for inputting/outputting the CML level signal simultaneously transfers two signals with different phases, it is insensitive to noise generated when signals are transferred. However, because of a relatively small swing range, the CML level signal cannot be used for an apparatus that should determine a logic level of data depending on a voltage level. That is, the CML level signal can be used for a clock signal, but cannot be used for other data signals.
Therefore, a CMOS level signal with a relatively large swing range is used for an apparatus for inputting/outputting a data signal. The CMOS level, similar to the CML level, means an average level determined by a predetermined DC level or a specific reference. The CMOS level signal is a signal toggling with predetermined amplitude or a predetermined swing range around a predetermined DC level called the CMOS level.
The CMOS level signal is different from the CML level signal in amplitude or a swing range based on the reference level.
In the above example, while a swing range of the CML level signal is approximately 0.5 V, the CMOS level signal is mainly a full swing signal, which swings between a power supply voltage VDD and a ground voltage VSS input to an apparatus, and thus has a relatively large swing range as compared with the CML level signal.
For example, in the above-described apparatus, when a power supply voltage VDD level is 1.5 V and a ground voltage VSS level is 0 V, the CMOS level signal has a swing range of 1.5 V about the CMOS level of 0.75 V.
Of course, the CMOS level signal should not necessarily be a full swing signal. However, since the CMOS level is mainly used for inputting/outputting a data signal, it has amplitude or a swing range enough to exactly determine a logic level with a variation of a voltage level.
Meanwhile, when a data signal is output from a semiconductor device, in particular, a synchronous dynamic random access memory (SDRAM), the data signal is generally synchronized with a clock. Similarly, when a data signal is input to the SDRAM, the data signal should be synchronized with a clock. That is, as described above, a data signal swinging about a CMOS level should be synchronized with a clock signal swinging around a CML level in order to perform an input or output operation.
Therefore, an input/output buffer of the SDRAM includes a CML-CMOS converter for converting a CML level signal into a CMOS level signal.
FIG. 1 is a circuit diagram of a conventional CML-CMOS converter for converting a CML level signal into a CMOS level signal. Referring to FIG. 1, a conventional CML-CMOS converter 100 has a structure of a general OP amplifier.
Specifically, the CML-CMOS converter 100 includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and first and second PMOS transistors P1 and P2. The first NMOS transistor N1 has a gate receiving a CML level signal CML_S, a drain connected to a driving node DN, and a source connected to a common node COMN. The first NMOS transistor N1 controls an amount of current flowing between the driving node DN and the common node COMN in response to the CML level signal CML_S. The second NMOS transistor N2 has a gate receiving a CML level inversion signal CML_SB, a drain connected to an output node OUT_ND, and a source connected to the common node COMN. The second NMOS transistor N2 controls an amount of current flowing between the output node OUT_ND and the common node COMN in response to the CML level inversion signal CML_SB. The third NMOS transistor N3 has a gate receiving a bias voltage BIAS, a drain connected to the common node COMN, and a source connected to a ground voltage (VSS) terminal. The third NMOS transistor N3 controls connection between the common node COMN and the ground voltage VSS terminal in response to the bias voltage BIAS to supply a sink current to the common node COMN. The first and second PMOS transistors P1 and P2 are connected in a current mirror configuration between the driving node DN and the output node OUT_ND to supply a source current to the driving node DN and the output node OUT_ND and simultaneously to control such that the same amount of current flows therethrough.
An operation of the conventional CML-CMOS converter 100 for converting the CML level signal into the CMOS level signal will now be described.
The first and second NMOS transistors N1 and N2 control an amount of current flowing between the driving node DN and the common node COMN and an amount of current flowing between the output node OUT_ND and the common node COMN in response to a level of a CML level signal CML_S and a level of a CML level inversion signal CML_SB, respectively. The level of the CML level signal CML_S always has a phase opposite to the level of the CML level inversion signal CML_SB. Thus, when the level of the CML level signal CML_S increases, the CML level inversion signal CML_SB decreases. Therefore, a driving force of the first NMOS transistor N1 increases to thereby increase an amount of current flowing between the driving node DN and the common node COMN while a driving force of the second NMOS transistor N2 decreases to thereby decrease an amount of current flowing between the output node OUT_ND and the common node COMN. That is, a voltage level of the driving node DN decreases while a voltage level of the output node OUT_ND increases.
On the other hand, when the level of the CML level signal CML_S decreases, the level of the CML level inversion signal CML_SB increases. Therefore, an amount of current flowing between the driving node DN and the common node COMN decreases while an amount of current flowing between the output node OUT_ND and the common node COMN increases. That is, a voltage level of the driving node DN increases while a voltage level of the output node OUT_ND decreases.
The CML-CMOS converter 100 amplifies the CML level signal CML_S as much as an amplification rate determined by sizes of its internal transistors (the first to third NMOS transistors N1, N2 and N3 and the first and second PMOS transistors P1 and P2) to output the amplified signal as a CMOS level signal CMOS_S.
However, since the CML-CMOS converter 100 is supplied with the power supply voltage VDD and the ground voltage VSS, a level of the CMOS level signal CMOS_S output through the output node OUT_ND cannot deviate from the level between the power supply voltage VDD and the ground voltage VSS. At the same time, because of a threshold voltage VTH of the third NMOS transistor N3 for supplying a sink current to the common node COMN, the level of the CMOS level signal CMOS_S output through the output node OUT_ND cannot decrease below a threshold voltage VTH level of the third NMOS transistor N3 added to the level of the ground voltage VSS level.
That is, the CMOS level signal CMOS_S output through the output node OUT_ND of the CML-CMOS converter 100 has a waveform as shown in FIG. 2.
FIG. 2 is a timing diagram of signals according to operation of the conventional CML-CMOS converter of FIG. 1.
Referring to FIG. 2, in a waveform of a signal according to an operation of the conventional CML-CMOS converter 100, the CMOS level signal CMOS_S is not disposed in a center between the power supply voltage VDD and the ground voltage VSS, but inclines toward the power supply voltage VDD.
Specifically, when a power supply voltage VDD level is 1.5 V and a ground voltage VSS level is 0 V, the CML level signal CML_S swings with a swing range of 0.5 V about a CML level of 1.25 V, that is, between 1.5 V and 1 V.
When the amplification rate of the CMOS level signal CMOS_S generated by amplifying the CML level signal CML_S is appropriately adjusted, the maximum level reaches 1.5 V of the power supply voltage VDD. However, the minimum level cannot reach 0 V of the ground voltage VSS and is maintained at 0.3 V, which is the threshold voltage level VTH of the third NMOS transistor N3. That is, the CMOS level signal CMOS_S swings between 1.5 V and 0.3 V.
Therefore, the CMOS level of the CMOS level signal CMOS_S output from the conventional CML-CMOS converter 100 is 0.9 V, which is higher than 0.75 V that is VDD/2.
However, the CMOS level signal CMOS_S output from the conventional CML-CMOS converter 100 is not used as an analog signal, but is converted into a digital signal that is determined as a logic ‘high’ or a logic ‘low’. That is, the CMOS level signal CMOS_S output from the CML-CMOS converter 100 is input to an inverter that uses a power supply voltage VDD and a ground voltage VSS as power and an output of the inverter is used.
The inverter is generally used in a semiconductor device and includes one NMOS transistor and one PMOS transistor. The logic determining level of the inverter is 0.75 V, half the difference between 1.5 V of the power supply voltage VDD and 0 V of the ground voltage VSS. The logic determining level is a reference level for determining which logic level of an input signal has logic ‘high’ or logic ‘low’. For example, when a signal of a voltage level lower than the logic determining level is input, a signal of a logic ‘low’ level (equal to VSS) is output, and when a signal of a voltage level higher than the logic determining level is input, a signal of a logic ‘high’ level (equal to VDD) is output.
When the CMOS level signal CMOS_S swinging about 0.9 V, which is an output signal of the conventional CML-CMOS inverter 100, is input to the above-mentioned inverter, its duty ratio is changed as compared with the case that the CMOS level signal CMOS_S that fully swings about 0.75 V is input.
That is, according to the conventional CML-CMOS converter 100, during an operation for converting the CML level signal CML_S into the CMOS level signal CMOS_S, the CMOS level cannot correspond to half the difference between the power supply voltage VDD level and the ground voltage VSS level, causing a change of a duty ratio of the CML level signal CML_S.